Yosys

1 device

Devices compatible with Yosys — open source Verilog synthesis framework for FPGA development without proprietary tools.

UPduino v3.1

FPGA

A low-cost, fully open source FPGA development board built on the Lattice ICE40UP5K with 5.3K LUTs, on-board FTDI FT232H USB programmer, 4MB qSPI flash, and 39 GPIO pins on PMOD-compatible headers.

Lattice ICE40UP5K (5.3K LUT FPGA)1Mbit SPRAM + 120Kbit DPRAM4MB39 GPIOWiFi NoBLE NoZigbee NoEthernet No

Fpga Development Digital Logic Education Risc V Soft Core prototyping

~$36View

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