UPduino v3.1
A low-cost, fully open source FPGA development board built on the Lattice ICE40UP5K with 5.3K LUTs, on-board FTDI FT232H USB programmer, 4MB qSPI flash, and 39 GPIO pins on PMOD-compatible headers.
$36.00
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Specifications
Components
Lattice iCE40 UltraPlus 5K FPGA with 5280 LUTs, 1Mbit SPRAM, 120Kbit DPRAM, and 8 DSP multiplier blocks. Ultra-low-power programmable logic supporting open source IceStorm toolchain.
FTDI FT232H Hi-Speed USB 2.0 to multipurpose UART/FIFO/SPI/I2C/JTAG bridge IC with Multi-Protocol Synchronous Serial Engine (MPSSE). Used for FPGA programming and debug.
Winbond 4MB (32Mbit) serial NOR flash memory with quad SPI (qSPI) interface for FPGA bitstream storage and configuration. Supports up to 133MHz clock speed.
Dedicated 12MHz on-board oscillator providing stable clock source for FPGA designs. Accessible via jumper R16 for optional disconnection.
Bus Interfaces
The UPduino v3.1 is a compact, affordable FPGA development board from tinyVision.ai designed around the Lattice iCE40 UltraPlus ICE40UP5K. With 5280 logic cells, 1Mbit of single-port RAM, 120Kbit of dual-port RAM, and 8 DSP multiplier blocks, it provides enough resources for meaningful FPGA projects including RISC-V soft processor implementations, custom peripheral controllers, and digital signal processing experiments. The board exposes all 32 FPGA GPIO pins plus additional signals across two 24-pin 0.1-inch headers, giving makers direct access to every I/O the chip offers.
Programming is handled by an on-board FTDI FT232H Hi-Speed USB bridge connected via Micro-USB, eliminating the need for an external programmer. The FT232H's Multi-Protocol Synchronous Serial Engine (MPSSE) supports SPI and JTAG modes, making it compatible with both the open source IceStorm toolchain and Lattice's proprietary tools. A 4MB Winbond qSPI flash chip stores FPGA bitstreams with support for quad-SPI mode for faster configuration loading, while a dedicated 12MHz oscillator (accessible via jumper R16) provides a stable clock source for designs that need precise timing.
The v3.1 revision improves on earlier versions with a more durable USB connector and PTC fuse protection replacing the original ferrite bead. The four-layer PCB features a solid ground plane and proper decoupling for clean signal integrity. Power comes from on-board 3.3V and 1.2V regulators that can also supply external circuits with up to 200mA at 3.3V. The entire board design is open source, created in KiCAD with schematics and layout files published on GitHub under the MIT license, making it a genuinely open hardware platform from silicon to PCB.
The UPduino v3.1 is fully compatible with the open source FPGA ecosystem including Yosys for synthesis, nextpnr for place-and-route, and APIO for project management. Its PMOD-compatible header layout allows direct connection of standard PMOD peripheral modules. The board ships with a blinking LED demo pre-loaded and includes two 24-pin header strips for soldering. At $36, it is one of the most accessible entry points into open source FPGA development.
Use Cases
4FPGA Development
FPGA learning, prototyping, and digital logic design using programmable hardware.
Digital Logic Education
Teaching and learning digital logic design, HDL programming, and computer architecture fundamentals.
RISC-V Soft Core
Implementing RISC-V processor cores in programmable logic for custom CPU design and experimentation.
Prototyping
Rapid hardware prototyping and proof-of-concept development with breadboard-friendly form factors and accessible development environments.
Resources
Where to Buy
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