Filter by CPU architecture
120 categories · 781 devices total
Cadence Xtensa LX7 32-bit processor architecture used in the ESP32-S3 series with AI vector extensions.
Cadence Xtensa LX6 32-bit processor architecture used in the ESP32 classic series.
ARM Cortex-M4F 32-bit processor with hardware floating-point unit, used in Nordic nRF52 and STM32 series.
RISC-V is an open-source instruction set architecture based on reduced instruction set computing principles.
Dual-core Tensilica Xtensa LX6 architecture in ESP32 running at up to 240MHz.
32-bit RISC-V open instruction set architecture for IoT and embedded microcontrollers.
Atmel AVR 8-bit RISC architecture used in classic Arduino boards. Simple, well-documented, and widely supported in education.
ARM Cortex-A55 is a high-efficiency 64-bit ARMv8.2-A application processor core with NEON SIMD and optional cryptographic extensions, commonly used in mid-range SoCs for edge computing and IoT gateways.
ARM Cortex-M4 processor architecture with hardware floating-point unit and DSP instructions, commonly used in embedded systems.
ARM Cortex-A7 is an energy-efficient 32-bit processor core, often used in IoT and embedded Linux applications.
ARM Cortex-M3 processor core — a 32-bit RISC CPU designed for microcontroller applications with low power consumption and deterministic real-time performance.
Dual-architecture processor supporting both ARM Cortex-M33 (ARMv8-M) and RISC-V Hazard3 cores, switchable at boot time.
ARM Cortex-M33 processor architecture with DSP and optional FPU, used in RP2350 and similar microcontrollers
Not applicable — this entry is a sensor module or display without a primary CPU architecture.
Heterogeneous architecture with ARM Cortex-A7 application core and RISC-V MCU co-processor
Espressif Xtensa LX6 32-bit dual-core processor used in ESP32 classic.
Heterogeneous architecture with triple-core ARM Cortex-A7 application cores and Cortex-M0 MCU co-processor
ARM Cortex-M series processor architecture for real-time embedded control.
Dual-core Tensilica Xtensa LX7 architecture in ESP32-S3 running at up to 240MHz with AI instructions.
Espressif Xtensa LX7 single-core processor variant used in ESP32-S2.
ARM Cortex-M0+ is an ultra-low-power 32-bit processor core designed for energy-efficient IoT and embedded applications.
Dual-architecture RP2350 chip supporting either ARM Cortex-M33 or RISC-V Hazard3 cores at 150MHz, selectable at boot.
Single-core 32-bit RISC-V architecture used in the ESP32-C3 at 160MHz.
64-bit RISC-V open instruction set architecture with General and Compressed extension support, used in Linux-capable SoCs.
ARM big.LITTLE architecture combining high-performance Cortex-A72 cores with efficient Cortex-A53 cores for balanced performance and power consumption.
64-bit ARM Cortex-A76 application processor architecture, used in Raspberry Pi 5 for high-performance computing workloads.
ARM1176JZF-S ARMv6 architecture used in the Broadcom BCM2835 (Raspberry Pi Zero W).
MIPS 24KEc is a 32-bit RISC processor core commonly found in router and gateway SoCs, featuring hardware multiply/divide, DSP extensions, and configurable cache.
Tensilica L106 32-bit single-core RISC processor at 80/160MHz used in ESP8266.
Espressif Xtensa LX7 32-bit dual-core processor with improved performance over LX6.
64-bit ARM Cortex-A53 application processor architecture used in Raspberry Pi Zero 2W and Raspberry Pi 3.
Dual-core ARM Cortex-M4 main processor with Cortex-M0+ co-processor.
Acconeer proprietary radar processor architecture used in 60GHz pulsed coherent radar sensor chips.
Digital Signal Processor architecture for signal processing applications.
Lattice ECP5 FPGA programmable logic architecture — not a fixed CPU, but capable of implementing soft-core processors including RISC-V via open-source toolchains.
Lattice iCE40 family of ultra-low-power FPGAs. Programmable logic devices supporting open source toolchains like IceStorm/Yosys.
Hybrid architecture with RISC-V and ARM processor cores on the same chip.
Semtech proprietary processor architecture used in radio and sensor chips.
Proprietary processor architecture from Semtech or Texas Instruments.
Tensilica Xtensa LX6 processor architecture, inferred from the ESP32 platform but not explicitly confirmed by the manufacturer.
Heterogeneous dual-MCU architecture pairing an Espressif Xtensa LX6 (ESP32) for connectivity with a RISC-V processor (e.g. K210) for AI and compute workloads.